This invention generally relates to a semiconductor memory organization that requires less layout design step count, and to a semiconductor memory layout design technique.
There are semiconductor memories known as SRAMs (static random-access memories). Some SRAMs adopt a sense amplifier organization to achieve a high-speed data readout performance, wherein a word line transition detection circuit detects a change of the word line voltage and sends out an enable signal to a sense amplifier according to the result of the detecting operation. If one word line is selected, a memory cell connected to the selected word line is read. Data, stored in that memory cell, is transferred to a pair of bit lines. Concurrently with this, a word line transition detection signal line is driven to report such a word line selection. On the basis of a signal received on the detection signal line, a sense enable signal generation circuit generates a sense enable signal. As soon as a stored-data dependent potential difference occurs between the bit lines, a sense amplifier amplifies such a difference.
The timing of sense enable must be optimized to the timing of data readout from a memory cell. If the sense enable timing is too fast, wrong data is provided. If it is too slow, fast data readout is impossible. Therefore, the delay time of the sense enable signal generation circuit is determined to obtain the best sense enable timing. For the case of usual SRAMs, the parasitic capacitance (unwanted adjunct) of each bit line and the parasitic capacitance of a word line transition detection signal line differ from each other. Accordingly, the difference between the elapsed time from word line selection to potential difference occurrence and the elapsed time from word line selection to sense enable signal generation must be "absorbed" within a sense enable signal generation circuit.
The specification change may involve the memory capacity change (i.e., the word count change). Deviations from the best sense enable timing cannot be avoided by changing only the memory cell count and the word line transition detection circuit count. This is because that the parasitic capacitance of each bit line does not vary with that of a word line transition detection signal line. Conventionally, the organization of sense enable signal generation circuits must be redesigned, when the layout design is required due to the specification change, to correct the timing of sense enable.
Recent development in computer-aided-design (CAD) is remarkable. For example, SRAM layout design uses a CAD program called a memory generator according to which an SRAM is divided into plural circuit blocks such as memory cells and sense amplifiers. Plural leaf cells holding internal organization descriptions of the circuit blocks are provided. The SRAM layout design is made by arranging the number of leaf cells corresponding to a given memory capacity.
If an attempt is made to use a memory generator in layout-designing the above-described SRAM adopting a sense amplifier organization, this requires the provision of leaf cells for sense enable signal generation circuits of several different types having different delay times. Of all the leaf cells one leaf cell suitable for a given memory capacity is selected. The organization of the selected one must be corrected fully. This produces such problems that the amount of leaf cell data increases, that memory generator programs become complicated, and that memory development degradation occurs.